An equalize circuit is used for bit lines of a semiconductor memory device. Especially when the potential of a bit line targeted for data reading and the potential of a bit line that serves as a comparison reference for the bit line targeted for data reading are amplified by a differential-type sense amplifier and read or refreshed in a DRAM (dynamic random access memory) or the like, it is necessary to equalize the bit lines so that a potential difference between the bit lines is eliminated before data is read onto the bit line from a memory cell.
FIG. 1 of Patent Document 1 and description of FIG. 1 describe high-speed equalization using a signal φEQL as a gate control signal for an equalize transistor 13. The signal φEQL has been level converted to a voltage higher than an externally applied supply voltage by a level conversion circuit 16.
Patent Document 2 describes that power consumption in a standby state can be reduced, and an operation speed in an active state can be improved by switching a substrate bias of an NMOS transistor between the active state and the standby state and varying the threshold value of the NMOS transistor in a semiconductor device such as a DRAM or an SRAM, including NMOS transistors.    [Patent Documents 1] JP Patent Kokai Publication No. JP-A-7-130175, which corresponds to U.S. Pat. No. 5,689,461.    [Patent Documents 2] JP Patent Kokai Publication No. JP-A-6-89574, which corresponds to U.S. Pat. No. 5,557,231.